Lead Principal Engineer Formal Verification (f/m/div)
Description
Your Role
Key responsibilities in your new role
As a Lead Principal Engineer for Formal Verification you will define and lead the formal verification strategy for the Automotive Microcontroller platforms.
- Work closely with platform architects and design leads to establish formal-friendly platform and design rules
- Establish formal verification as a standard method in IP verification
- Guide the use of formal verification so that correct formal techniques are used appropriately to improve efficiency of IP and product level verification
- Grow formal verification experts within Automotive Microcontrollers (ATV MC) business line and establish a Formal Verification Community
- Push the boundaries of the application of formal verification in Digital Mixed Signal and Power Aware Verification
- Standardize and automate the use of formal verification, including through the practical application of AI techniques
Your Profile
Qualifications and skills to help you succeed
You are a leader in Formal Verification with a strong track record of driving complex initiatives through strategic, multi‑angle problem analysis. You leverage deep expertise, strong networks, and exceptional communication skills to deliver innovative solutions, influence stakeholders, and foster effective cross‑functional collaboration.
- A University Degree within STEM (Science, Technologies, Engineering and Mathematics) area
- At least 12 years of relevant work experience with 5+ years of experience in the use of formal verification
- A deep understanding of formal verification, including the effective use of techniques such as abstraction, non-determinism, invariants, and assume‑guarantee reasoning, combined with a solid understanding of formal engines and how to apply them most effectively
- A broad experience applying formal verification across multiple domains, including the verification of algorithms, protocols, and design blocks, its use in SoC verification, and the efficient integration of formal methods within hybrid simulation‑formal environments
- The ability to excite and enable verification engineers to use formal methods
- Significant internal and external contributions in the use of formal verification, and can provide evidence of pushing the use of formal verification into new areas
- A footprint demonstrating influence on the use of formal verification in industry and academia
Contact:
Francisca Dias, LinkedIn
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